Miniaturization constitutes a continuing interest in designing and fabricating semiconductor devices. For example, it can be advantageous to decrease the size of memory cells used in integrated circuit memory devices. Those of ordinary skill know of a variety of configurations that are an attempt to decrease cell size. However, a disadvantage of some conventional configurations includes complicated structures that use a complicated process flow for fabrication. Also, another disadvantage includes interface size and connectivity problems between the complex conductive and semiconductive structures that become increasingly problematic as cell size decreases.
Accordingly, a need exists in the art for cell designs and fabrication methods that decrease cell size without unnecessarily complicating cell design and/or process flows.